Departmental Bulletin Paper 回路に関する付加情報を用いた検証の高速化とビット幅推定の正確さ向上に関する研究(2)(学内特別研究)

中村, 一博  ,  Kazuhiro, Nakamura

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This report presents an improvement of bit-width estimation accuracy of control-path of sequential logic circuit with supplemental information on the circuit. We demonstrate a bit-width estimation method for reducing area of digital comparators.
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http://mlib.nit.ac.jp/webopac/bdyview.do?bodyid=TC00535312&elmid=Body&fname=45_4_19.pdf

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