Conference Paper Throttling Control for Bufferless Routing in On-Chip Networks

Yicheng Guan  ,  Cisse Ahmadou Dit ADI  ,  Takefumi Miyoshi  ,  Michihiro Koibuchi  ,  Hidetsugu Irie  ,  Tsutomu Yoshinaga  ,  イェチェング ガン  ,  シセ アマドウ ディ アデイ  ,  タケフミ ミヨシ  ,  ミチヒロ コイブチ  ,  イリエ ヒデツグ  ,  ツトム ヨシナガ

2012 IEEE 6th International Symposium on Embedded Multicore SoCs (MCSoC-12)pp.37 - 44 , 2016-09-12 , IEEE
As the number of core integration on a single die grows, buffers consume significant energy, and occupy chip area. A bufferless deflection outing that eliminates router’s input port buffers can considerably help saving energy and chip area while providing similar performance of xisting buffered routing, especially for low-to-medium network loads. However when congestion increases, the bufferless frequently causes flits deflections, and misrouting leading to a degradation of network performance. In this paper, we propose IRT(Injection Rate Throttling), a ocal throttling mechanism that reduces deflection and misrouting for high-load bufferless networks. IRT provides injection rate control independently for each network node, allowing to reduce network congestion. Our simulation results based on a cycle-accurate simulator show that using IRT, IRT reduces average transmission latency by 8.65% compared to traditional bufferless routing.

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