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Research on a High Performance LDO Regulator Operating with Low-Power and Low-Supply-Voltage
低消費電力・低電圧動作が可能な高性能シリーズレギュレータに関する研究
2009/9/30
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The research presented in this dissertation is focused on the designof a high performance Low Dropout Regulator (LDO) which targetedfor low-power and low-voltage electronic appliances.Recently, with the increase in power consumption of portable electronicappliances, low power and high performance LDO is required.High accuracy of output voltage, high speed response and low noisehave become the main keywords for the researchers. To meet theabove mentioned requirements, several advanced techniques are proposedand presented in this dissertation to design a high performanceLDO with fast load transient response, high power supply rejectionratio, small inrush current, good load Regulation and precise overcurrent protection.Firstly, a Quick Response Circuit has been proposed to achieve fastload transient response when load current abruptly changes. The circuithas been achieved through properly charging and discharging thegate capacitor of power MOSFET. Secondly, a Bulk-Gate Control Circuithas been proposed to realize the high power supply rejection ratio(PSRR). The circuit has been achieved through controlling the bulkgateof input transistor of error amplifier. Thirdly, in order to keepthe LDO output voltage drop due to bonding wire, the CompensatedCircuit has been proposed. It works to adjust the feedback voltage offeedback network. Fourthly, an Auto Inrush Current Limiting Circuithas also been proposed to restrain the inrush current of output capacitorto make sure that the malfunction of the application system dueto inrush current is avoided. Not only the small inrush current butalso the high speed start up of LDO has been achieved. Fifthly, anOver Current Protection Circuit which is necessary to protect LDOfrom the damage happened by over load current or output shortening,is proposed. The proposed protection circuit has high accurate limitingcurrent and stable holding current without getting effects fromlatchup.The high performance LDO with proposed Quick Response Circuit,Bulk-Gate Control Circuit, Compensated Circuit was fabricated with0.18m CMOS technology while the LDO with proposed Over CurrentProtection Circuit was fabricated with 0.35m CMOS technology. Forthe proposed Auto Inrush Current Limiting Circuit, the implementedchip is now being fabricated.The experimental results of the fabricated chips show that the outputundershoot and overshoot of load transient response are only116mV and 104mV for 4.7F output capacitor and ILOAD=0.1mA() 150mA. Also, the PSRR performance is up to 75dB for 10Hz andremaining high 61.8dB for 1KHz ripple frequency for VOUT = 1:2Vand ILOAD = 50mA. The output voltage drop is restrained to lessthan 1% even when the load current reaches 150mA. The quiescentcurrent of the whole chip is 8.5A for no load and 35A for full loadcurrent. Meanwhile, the LDO with proposed Over Current ProtectionCircuit has a high accurate limiting current of 200mA and a stableholding current of 17.8mA. It can digitally shut down the output ofLDO, thus, the latchup effect is avoided.From the simulation results, the LDO with Auto Inrush Current LimitingCircuit can achieve a very small inrush current of 144.1mA andfast start up time of 127.7s for 10F output capacitor.With all the proposed and developed circuits applied, an LDO withextremely low-power consumption, low-operation-voltage but excellentcharacteristics can be achieved.In recent year, with the rapid development of system-on-chip designs,there is a growing trend toward power-management integration. Thelocal LDO which are utilized to power up sub-blocks of a system individuallymust be the On-chip. However, the external capacitors ofLDO have the equivalent series resistance (ESR) and they can adverselyaffect the stability of the regulator. In addition, these capacitorsand their external pins required to mount, increase the surfacearea (space) which will result in the increasing of high cost for massproduction. Hence, the design of a low-voltage high-stability and fasttransientLDO with, preferably, capacitor-free operation has becomeone of the main topic in our future works. Moreover, for present LDO,the Power MOSFET occupies the majority of the chip area. With theadvance CMOS technology scaling, the driving ability of Power MOSFETat the same size improves compared with the past. Concretely,with the scaling of CMOS technology, the leak current will remarkablyflow in the circuit. Hence, the research on a design of an LDOwhich can correspond to such the Power MOSFET is the one of themost important task to be done.電気通信大学博士学位論文 学位の種類：博士（工学）（課程） 学位授与年月日：平成２１年９月３０日
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| 日付 |
2010-08-26T01:54:22Z
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| 国立情報学研究所 メタデータ主題語彙集（資源タイプ） |
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| 言語 |
en
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