会議発表論文 New Measurement Base De-embedded CPU Load Model for Power Delivery Network Design

Okano, Motochika  ,  Watanabe, Koji  ,  Naitoh, Masamichi  ,  Omura, Ichiro

pp.2288 - 2293 , 2015-06 , IEEE
ISSN:2150-6086
内容記述
CPU load model including on-chip wiring and package interconnection has been required for printed circuit board (PCB) design of digital products according to the improvement in the speed of CPU operation in recent years. Especially, accurate power delivery network (PDN) information inside CPU is indispensable for PCB design according to requirement of low-impedance and the broadband (from DC to GHz) from the inside of CPU to DC-DC converter. While the detailed impedance information inside CPUs is not disclosed to PCB board designers with the complicated back-end and front-end production design for CPU chip and package. This paper aims to establish new methodology to extract CPU load model with combination of measurement and simulation. The method is simple yet powerful for high-end CPU board design.
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http://ds.lib.kyutech.ac.jp/dspace/bitstream/10228/5794/1/nperc62.pdf

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