Departmental Bulletin Paper フィードフォワード型ジッタシェーパーDAC の 試作と評価

峯村, 亮佑

Description
We present a novel delta–sigma digital-to-analog converter using a jitter shaper to reduce the noise caused by clock jitter. Intermodulation between the quantization noise and clock jitter produces wide spectrum noise,which degrades the signal-to-noise ratio (SNR) of the delta-sigma DAC. The accuracy of the delta-sigma DAC is determined by the jitter; it is improved by reducing the effects of jitter. The delta-sigma DAC requires jitter compensation for SNR degradation caused by clock jitter. The jitter shaper can reduce noise in the signal band by shaping the noise caused by the clock jitter. It is designed for a 0.18 µm complementary metal-oxidesemiconductor (CMOS) and comprises switched capacitor and sample-and-hold circuits. We implement and measure the DAC with a jitter shaper circuit. The complete system is implemented on a single chip that is fabricated with a 0.18 μm CMOS technology for a 1.8 V operation with a die size of 6.25 mm².Key Words : D/A converter, delta-sigma modulator, jitter shaper
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http://repo.lib.hosei.ac.jp/bitstream/10114/13551/1/15R3138.pdf

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