紀要論文 ジッタシェーピング型 ΔΣDAC と試作

渡邉, 裕紀

内容記述
We present a novel delta-sigma digital-to-analog converter (DSDAC) using a jitter shaper to augment the noise caused by clock jitter. The jitter shaper is designed for a 0.18 µm CMOS and comprises switched capacitor and sample-and-hold circuits. We simulate the DSDAC in MATLAB/simulink and design and simulate the complete jitter shaper circuit in Virtuoso/spector. We predict that the jitter shaper willimprove the signal-to-noise ratio (SNR). We had the A to the integrated circuit and measured the DSDAC combined with FPGA. Key Words : D/A converter, delta-sigma modulator, jitter shaper, clock jitter, IC.
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https://hosei.repo.nii.ac.jp/?action=repository_action_common_download&item_id=13090&item_no=1&attribute_id=22&file_no=1

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