We present a novel delta-sigma digital-to-analog converter (DSDAC) using a jitter shaper to augment the noise caused by clock jitter. The jitter shaper is designed for a 0.18 µm CMOS and comprises switched capacitor and sample-and-hold circuits. We simulate the DSDAC in MATLAB/simulink and design and simulate the complete jitter shaper circuit in Virtuoso/spector. We predict that the jitter shaper willimprove the signal-to-noise ratio (SNR). We had the A to the integrated circuit and measured the DSDAC combined with FPGA. Key Words : D/A converter, delta-sigma modulator, jitter shaper, clock jitter, IC.