紀要論文 ジッタシェーピング型 ΔΣDAC と試作

渡邉, 裕紀

57pp.1 - 8 , 2016-03-24 , 法政大学大学院 理工学・工学絵研究科
ISSN:2187-9923
内容記述
We present a novel delta-sigma digital-to-analog converter (DSDAC) using a jitter shaper to augment the noise caused by clock jitter. The jitter shaper is designed for a 0.18 µm CMOS and comprises switched capacitor and sample-and-hold circuits. We simulate the DSDAC in MATLAB/simulink and design and simulate the complete jitter shaper circuit in Virtuoso/spector. We predict that the jitter shaper willimprove the signal-to-noise ratio (SNR). We had the A to the integrated circuit and measured the DSDAC combined with FPGA. Key Words : D/A converter, delta-sigma modulator, jitter shaper, clock jitter, IC.
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http://repo.lib.hosei.ac.jp/bitstream/10114/12421/1/14R3142%e6%b8%a1%e9%82%89%e8%a3%95%e7%b4%80.pdf

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