Speeding up a Communications System with Check Sum Operation Circuits and Special Instructions
井上, 雄策INOUE, Yusaku
102015-03-24 , 法政大学大学院情報科学研究科
In recent years, the communication amount of data processed with CPU are increasing by high definition of a picture. There are researches which focused to accelerate TCP/IP processing or used Network Processing Unit. In this paper, we tried to solve it by designing hardware which is focused on instructions. We designed the Check Sum calculation circuit which is used for detecting errors when sending and receiving data to process it at CPU frequency. Moreover we designed spacial instructions which don’t access stacks of the CPU. For the special instructions, we made compiler in JavaCC(Java Compiler Compiler). This special instructions reduce movement clocks of communication data by writing and reading the data directly to the ethernetcontroller which controls sending and receiving packets. We emphasize not only design but also implementation because there are many cases that hardware implementation goes wrong even if simulation looks like correct processing. For implementing our circuits , we chose DE2-115 developed by Altera because this boards provide various interfaces.