FPGA Implementation of Writable Image Acquisition System at High Speed to SD Card
福田, 龍宙FUKUDA, Tatsuoki
102015-03-24 , 法政大学大学院情報科学研究科
In recent years, hardware/software co-design has become important. In particular, the development of a composite device of high performance I/O interface by using FPGA become popular. We designed and implemented a hardware system by focusing on two devices of Camera and SD Card. Specifically, we designed a system that can collectively be processed from the acquisition of the image to be taken to store in the data. Moreover, we tried to speed up the data transfer by the control of the SDRAM because it can be controlled without a burden on the transfer rate when there is a change in capacity of the image data. First step is the design of the Camera Interface, LCD Controller, SDRAM Controller, SD Card Controller, VGA Controller, and CPU. Second step is the implementation of the whole system which using the SOPC Builder and the Quartus IIdevelopment tool. More specifically, the real-time image data is received through the Camera Interface from a camera of tPad. It was controlled by the SD Card Controller and was stored in the SD Card after passing through the Avalon Bus. In addition, the stored in image files are outputted into VGA Display. This paper expresses the integration from the acquisition of the image to the data storage and the speed of the data transfer.