Journal Article Optimizing silicon avalanche photodiode fabricated by standard CMOS process for 8 GHz operation

Zul, Atfyi Fauzan M. N.  ,  Iiyama, Koichi  ,  Gyobu, Ryoichi  ,  Hishiki, Takuya  ,  Takeo, Maruyama

(7289585)  , pp.99 - 102 , 2015-10-05 , Institute of Electrical and Electronics Engineers Inc.
Silicon avalanche photodiode (APD) was fabricated by standard 0.18 μm CMOS process. The current-voltage characteristic and frequency response was measured for the APD with and without guard ring. With the guard ring around the perimeter of the diode junction, it shows a better performance for the maximum bandwidth but in contrast lower in responsivity. To enhance the bandwidth, the detection area and the PAD size for RF probing are optimized to 10 × 10 μm2 and 30 × 30 μm2, respectively, to decrease the device capacitance, the spacing of interdigital electrode is narrowed to 0.84 μm to decrease carrier transit time, and by cancelling the carriers photo-generated in the deep layer and the substrate because the carriers are slow diffusion carriers. As a result, the maximum bandwidth of 8 GHz was achieved along with a gain-bandwidth product of 280 GHz. © 2015 IEEE.

Number of accesses :  

Other information