Journal Article A Design of 0.7-V 400-MHz All-Digital Phase-Locked Loop for Implantable Biomedical Devices

Matsuoka, Toshimasa  ,  Bae, Jungnam  ,  Radhapuram, Saichandrateja  ,  Jo, Ikkyun  ,  Wang, Weimin  ,  Kihara, Takao

99-C ( 4 )  , pp.431 - 439 , 2016-04-01 , 電子情報通信学会 , The Institute of Electronics, Information and Communication Engineers , デンシ ジョウホウ ツウシン ガッカイ
A low-voltage controller-based all-digital phase-locked loop (ADPLL) utilized in the medical implant communication service (MICS) frequency band was designed in this study. In the proposed design, controller-based loop topology is used to control the phase and frequency to ensure the reliable handling of the ADPLL output signal. A digitally-controlled oscillator with a delta-sigma modulator was employed to achieve high frequency resolution. The phase error was reduced by a phase selector with a 64-phase signal from the phase interpolator. Fabricated using a 130-nm CMOS process, the ADPLL has an active area of 0.64 mm^2, consumes 840 µW from a 0.7-V supply voltage, and has a settling time of 80 µs. The phase noise was measured to be -114 dBc/Hz at an offset frequency of 200 kHz.
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