Journal Article An offset distribution modification technique of stochastic flash ADC

Asano, Tomohiro  ,  Hirai, Yusaku  ,  Tani, Sadahiro  ,  Yano, Shinya  ,  Jo, Ikkyun  ,  Matsuoka, Toshimasa

13 ( 6 )  , pp.1 - 10 , 2016 , 電子情報通信学会 , デンシ ジョウホウ ツウシン ガッカイ , The Institute of Electronics, Information and Communication Engineers
A new non-linearity reduction technique for stochastic flash ADC (SF-ADC) is proposed, focusing on distribution of comparator input-referred offsets. The SF-ADC test chip fabricated in a 130-nm CMOS process demonstrated the proposed technique can improve SNDR. In addition, the digital re-quantization also can improve the linearity more, where quantization level and fractional correction can be optimized using genetic algorithm.

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