学術雑誌論文 ANALYSIS OF A CONTROLLER-BASED ALL-DIGITAL PHASE-LOCKED LOOP

Radhapuram, Saichandrateja  ,  Bae, Jungnam  ,  Jo, Ikkyun  ,  Wang, Weimin  ,  Matsuoka, Toshimasa

15 ( 1 )  , pp.57 - 73 , 2015-09 , Pushpa Publishing House
ISSN:09737006
内容記述
A design procedure of an all-digital phase-locked loop (ADPLL) based on phase selection mechanism with loop stability independent of process, supply voltage and temperature is presented. A poly-phase filter and a phase interpolator are used to generate multiple phases to reduce the phase error. The modeling of proposed ADPLL structure is extensively investigated and mathematically described. For a phase and a frequency step input change, the closed-loop system of the proposed ADPLL eliminates phase error. Time-domain response of the behavioral-level simulation of the proposed structure on 130-nm CMOS technology with 0.7V supply voltage reveals the presented analytical model.
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http://ir.library.osaka-u.ac.jp/dspace/bitstream/11094/52099/1/Far%20East%20J_1410719227.pdf

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