||A DYNAMIC LATCHED COMPARATOR WITH BUILT-IN OFFSET CALIBRATION
Matsuoka, Toshimasa ,
Tani, Sadahiro ,
Ohara, Kenji ,
Hirai, YusakuCui, Ji
Far East Journal of Electronics and Communications
115 , 2015-06 , Pushpa Publishing House
This paper presents a novel dynamic latched comparator that uses a built-in offset-cancellation technique. The proposed offset-cancellation scheme does not require any extra amplifiers or digital-assistant cancellation. Combining a conventional dynamic latched comparator with a one-stage amplifier benefits from not only an enhancement in comparator gain but also a reduction in power consumption. The Monte-Carlo simulation results, which were derived by using a 130‑nm CMOS process, show that the comparator achieved a 3.8 mV equivalent input-referred offset voltage at a 10 MHz clock rate while dissipating 2.7 μW from a 1.2V supply.