学術雑誌論文 A DYNAMIC LATCHED COMPARATOR WITH BUILT-IN OFFSET CALIBRATION

Cui, Ji  ,  Tani, Sadahiro  ,  Ohara, Kenji  ,  Hirai, Yusaku  ,  Matsuoka, Toshimasa

14 ( 2 )  , pp.105 - 115 , 2015-06 , Pushpa Publishing House
ISSN:09737006
内容記述
This paper presents a novel dynamic latched comparator that uses a built-in offset-cancellation technique. The proposed offset-cancellation scheme does not require any extra amplifiers or digital-assistant cancellation. Combining a conventional dynamic latched comparator with a one-stage amplifier benefits from not only an enhancement in comparator gain but also a reduction in power consumption. The Monte-Carlo simulation results, which were derived by using a 130‑nm CMOS process, show that the comparator achieved a 3.8 mV equivalent input-referred offset voltage at a 10 MHz clock rate while dissipating 2.7 μW from a 1.2V supply.
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http://ir.library.osaka-u.ac.jp/dspace/bitstream/11094/51765/1/FEJEC14_2_105.pdf

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