Journal Article Area Efficient Annealing Processor for Ising Model without Random Number Generator

GYOTEN, Hidenori  ,  HIROMOTO, Masayuki  ,  SATO, Takashi

E101.D ( 2 )  , pp.314 - 323 , 2018-02 , Institute of Electronics, Information and Communications Engineers (IEICE)
ISSN:0916-8532
Description
An area-efficient FPGA-based annealing processor that is based on Ising model is proposed. The proposed processor eliminates random number generators (RNGs) and temperature schedulers, which are the key components in the conventional annealing processors and occupying a large portion of the design. Instead, a shift-register-based spin flipping scheme successfully helps the Ising model from stucking in the local optimum solutions. An FPGA implementation and software-based evaluation on max-cut problems of 2D-grid torus structure demonstrate that our annealing processor solves the problems 10-10[4] times faster than conventional optimization algorithms to obtain the solution of equal accuracy.
Full-Text

http://repository.kulib.kyoto-u.ac.jp/dspace/bitstream/2433/229141/1/transinf.2017RCP0015.pdf

Number of accesses :  

Other information