Journal Article Statistical Timing Modeling Based on a Lognormal Distribution Model for Near-Threshold Circuit Optimization

SHIOMI, Jun  ,  ISHIHARA, Tohru  ,  ONODERA, Hidetoshi

E98.A ( 7 )  , pp.1455 - 1466 , 2015-07-01 , Institute of Electronics, Information and Communication Engineers(IEICE)
ISSN:0916-8508
NCID:AA10826239
Description
Near-threshold computing has emerged as one of the most promising solutions for enabling highly energy efficient and high performance computation of microprocessors. This paper proposes architecture-level statistical static timing analysis (SSTA) models for the near-threshold voltage computing where the path delay distribution is approximated as a lognormal distribution. First, we prove several important theorems that help consider architectural design strategies for high performance and energy efficient near-threshold computing. After that, we show the numerical experiments with Monte Carlo simulations using a commercial 28nm process technology model and demonstrate that the properties presented in the theorems hold for the practical near-threshold logic circuits.
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http://repository.kulib.kyoto-u.ac.jp/dspace/bitstream/2433/202109/1/transfun.E98.A.1455.pdf

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