||Statistical Timing Modeling Based on a Lognormal Distribution Model for Near-Threshold Circuit Optimization
SHIOMI, Jun ,
ISHIHARA, TohruONODERA, Hidetoshi
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
1466 , 2015-07-01 , Institute of Electronics, Information and Communication Engineers(IEICE)
Near-threshold computing has emerged as one of the most promising solutions for enabling highly energy efficient and high performance computation of microprocessors. This paper proposes architecture-level statistical static timing analysis (SSTA) models for the near-threshold voltage computing where the path delay distribution is approximated as a lognormal distribution. First, we prove several important theorems that help consider architectural design strategies for high performance and energy efficient near-threshold computing. After that, we show the numerical experiments with Monte Carlo simulations using a commercial 28nm process technology model and demonstrate that the properties presented in the theorems hold for the practical near-threshold logic circuits.